( 1.3 V) from the LEVEL pot via U4.
The bias adjust sets the amplifier
biasing voltage to a nominal -70 mV.
The counter may trigger on either
slope of the input signal. The SLOPE switch determines this by controlling
the output polarities of U2. When the switch is placed to +, the outputs of
U2 will be 180 degrees out of phase with their respective inputs.
opposite is true when the switch is placed to -.
The Input Trigger assembly provides additional amplification of the
input signals before they are sent to counting circuits. The amplifier has
a gain of about 3.5 and contains a Schmitt Trigger, which shapes the lower
frequencies into fast rise time square waves.
The trigger output is a
negative pulse about -0.6 V in amplitude.
An offset control at the
input to U4 corrects for offset voltages in U2 when the SLOPE switch
position is changed.
The output of U4 also connects to the U2 current
source and turns off the amplifier when the signal level exceeds + 3.5 Vdc.
b. Main Gate. The Main Gate assembly, shown in block format in figure
4, contains three primary blocks: Input Selector, Main Gate, and Scaler.
All input signals and reference signals (time base) are presented to the
Input Selector circuits which select only those signals needed to complete a
The Main Gate circuitry determines the precise moment
these signals are passed to the scalers and, in addition, sets the timing
requirements for a time interval measurement. The scalers count the input
pulses of both the input signal (events) and reference signal (time) and, at
the end of the gate time, outputs the stored data. A fourth block, Turn Off
Control at the lower left of figure 4, controls the existence of the 500 MHz
internal time base signal, as well as the Channel A and Channel B signals.
When the Frequency function is selected on the front panel, the input
Channel A signal is routed through the Channel A Multiplexer (U14).
passes the signal to the Event Gate Flip-Flop (U5) and to the Signal Gate
(U10). At the same time, the Channel C Multiplexer (U13) passes the 500 MHz
clock signal (time base) to the clock input of the Time Gate Flip-Flop (U7).
With both signals present on their respective flip-flops, a set of
conditions must be considered.
Both gate flip-flops have been set by the
Gate reset signal. Both U5 and U7 have High outputs which prevent the Event
binary (U4) and the time Binary (U2) from toggling. The T.I. & EVT Enable
Line is LOW and allows U10 to pass the input signal to the disabled U4.
At this time, the Gate Arm Line, from Gate Control to U5, goes High
permitting the next input pulse to toggle U5. This causes U4 to be enabled
and allows the next input pulse to pass through U4 to the Event