measurement being made. For example, in a period measurement, the division

needs to be

; therefore, no exchange is events needed, since time

data is in NR and events data is in DR.

In a frequency measurement,

however, the division needs to be

; therefore, the registers

must exchange their data to perform the correct division.

Shifting data from one register to another involves "reading" the data

out of each register, storing it in a latch, and then "writing" the data

back into the other register.

Once both groups of data are positioned in

their correct register, the Adder/Subtracter Register accomplishes the

division by performing a series of successive subtractions. Each time this

register completes a successful subtraction, it increments the Quotient

Multiplier Counter (QMC). Once this counter determines the total number of

successful subtractions in a particular digit, it transfers that data into

the Quotient Register (QR) and continues the subtraction process for the

next significant digit. After all subtractions are complete, the QR shifts

the data into the Denominator Register, where it can be distributed to the

display.

The Quotient Multiplier Storage (MS) circuit is used to determine the

unit multiplier (K, M, n, etc.) of the result.

The digit Storage (DS)

defines the number of significant digits to be computed. The Digit Counter

(DC) is compared with DS. When DS = DC, the division routine is complete.

The Decimal Point Locator for the Result (DPLR) is a counter that keeps

track of the decimal point location in the result.

The Decimal Point

Locator for K (DPLK) is also a counter and is used to keep track of decimal

point information from the plug-in.

f. State Control.

To this point, the counter has been described in

terms of signal or data flow. To control the intricacies of the data flow,

a hierarchy of commands and controls are needed. Depending on the operating

model being used, the counter uses a particular program which outputs the

commands to the various assemblies in the counter.

All possible program

steps are contained in the ROMs (Read Only Memories) located on the lower

left of the block diagram.

The flow within the program is determined by

generating a series of commands and then altering the program flow based on

the results.

The ROMs output two sets of program codes; one set when the MSB (Most

Significant Bit) address line is High and the other set when MSB is Low.

The first set is chosen by address codes, which selects one out of 128

possible ROM address locations. The second set of program codes is chosen

from a second set of ROM address locations. Each address location contains

a specific program code.

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