oscillator, which means that it is manually adjustable, or tunable.
This allows
the entire receiver system to be tuned to the frequency being received if the
transmitter drifts.
The 1-MHz signal is connected to the reference chassis
subassembly (B4) in the synthesizer. This assembly divides the frequency and puts
out a 100-kHz signal to three other subassemblies.
The tuning accuracy of the
receiver system is determined by comparing the phases of the 100-kHz received
carrier frequency and the stable 100-kHz internal reference frequency in the phase
comparator subassembly (B1).
The resultant output is a varying dc voltage whose
change is proportional to the phase difference of the two signals. This dc voltage
is fed to a panel-mounted zero-center-scale meter.
d. Output Frequencies.
(1) The 100-kHz signal from the reference chassis subassembly (B4) is fed to
the 100-kHz RF amplifier subassembly (A4) in the stabilizer.
The
amplified signal is then sent to the two converters of the AN/FRR-41 and
is also coupled to three subassemblies in the stabilizer.
Starting with
the highly stable 100-kHz signal as a reference, the 555-kHz stabilizer
subassembly (A1) produces an equally stable 555-kHz output frequency that
is coupled to the converters. In the same manner, the 17-MHz stabilizer
subassembly (A2) produces a 17-MHz output signal.
Notice, however, that
this signal is coupled to the two receivers as is the output of the
subassembly (A3).
The reference frequency produced by the 9-17 MHz
stabilizer subassembly (A3) is variable from 9 MHz to 17 MHz.
Its
frequency selection is controlled by the MHz change switch on the
stabilizer drawer.
(2) The reference chassis subassembly (B4) in the synthesizer also produces a
100-kHz reference frequency that is coupled to the variable frequency
oscillator (VFO) buffer and spectrum generator subassembly (B2).
There
are many outputs from this subassembly.
The actual synthesizer output
signal is derived from the 24.55-34.55 MHz shown leaving the right side of
the block.
This variable frequency is divided into a 2.455-3.455 MHz
output frequency by locked divider subassembly (B3) and is amplified and
fed to the two receivers. This reference frequency, more than any other,
determines the stability of the receiver because it replaces the VFO in
the receiver. If it is unstable the receivers will be unstable.
(3) The frequency of the VFO (B2) is controlled by a dc error voltage produced
by subassemblies B7, B6, B5, and B9 in the following manner: 24.55-34.55
MHz signal is coupled from the VFO buffer and spectrum generator
subassembly (B2) to the wideband amplifier subassembly (B7).
The
amplified signal is then mixed in the first balanced mixer subassembly
(B6) with a 28.90-to 38.90-MHz signal produced by subassembly B2.
The
mixer output is in the band between 4.350 and 4.449 MHz.
The front IF
subassembly (B5) in conjunction with the gear box subassembly (B9)
produces a stable reference frequency of 390 to 399 kHz. This is done by
multiplying and dividing the output of an oscillator and phase-locking it
to the 100-kHz pulses which the VFO (B2) generates from the highly stable
327 L2
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