wideband sampler A3.
The sampler is switched by pulse generator A2 at a
rate determined by the internal VFO, A7A3.
The sampler output represents
phase difference between the sampler switching time and the input frequency.
If the internal VFO harmonic is phase locked to the input frequency, the
sampler output will be a dc voltage proportional to phase error.
There are many harmonics of frequencies tunable within the internal
VFO range that will zero beat or phase lock with an input signal.
In
operation, the internal VFO can be tuned to any one of these. The sampler
output is amplified in the variable gain and dc amplifiers of A4. The gain
is set by front panel LEVEL ADJ control. The output of A4 goes to A5 and A6
assemblies. A5 dc amplifier provides the sampler output waveform at front
panel jack J2. A5 peak holding circuit develops a dc voltage proportional
to the amplitude of the beat signal from the sampler with pulsed RF input
signals. This level is amplified and applied to meter M1 when operating in
PULSED RF MODE.
In the APC mode the meter is switched directly to A4 dc
amplifier for reading the phase error of the phase-lock loop.
The variable-gain amplifier in A4 includes a reference voltage to
establish 0 phase error in the phase-lock error voltage loop. In the APC
mode, a 1 kHz oscillator is turned on and its signal is injected into the
phase-lock loop at the reference mode.
The 1 kHz signal appears at the
output of sampler A3 and is taken from this point by a 1 kHz filter, located
in A4, for amplification and level detection in assembly A6. If phase-lock
has not occurred, this signal is below the required detection level and the
signal to the counter is inhibited by the inhibit amplifier in A8.
Therefore, the counter readout is all zeros. When phase-lock is achieved,
the 1 kHz signal is above the required level, and the inhibit to the counter
is removed for a frequency readout.
In the PULSED RF mode the inhibit
amplifier is biased to continually pass the counter input signal.
The feedback loop output of the variable gain amplifier goes through a
range compensation circuit in A6, which connects to VFO linearizer A7A1.
Range compensation is varied in steps with the range switch for optimum
phase-locking from 0.05 to 18 GHz. The linearizer compensates for the non-
linear VFO gain characteristics over the tuning range.
In the PULSED RF
mode, the feedback loop is disabled in the linearizer. Linearizer output is
a dc voltage applied to VF0 control A7A2. Voltage controlled capacitors in
VFO control A7A2 hold the VFO frequency in phase lock when in the APC mode.
Thus, the APC loop is completed.
VFO A7A3 is tunable between 66.7 to 133.3 MHz and its output goes to
two buffers. The first buffer provides input to pulse driver A1 when the
Model 5257A is switched to the frequency ranges above 200 MHz. The second
buffer provides VFO input to a divide-by-four prescaler A8.
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