Scaler.
It also enables U7 which allows the next 500 MHz clock pulse to
toggle U7 and in turn enable U2. This allows the clock signal to enter the
Time Scaler. The event and time pulses are each divided by 10 before being
passed to the scaler circuits.
In the Totalize mode, the counter will totalize Channel A pulses for
as long as the function switch remains in the Start position.
In this
position the Channel C Multiplexer (U13) is disabled from passing the 500
MHz clock signal.
U12B is, as a result, enabled to pass the Channel B
signal (totalize can be A+B or A-B). The Channel B signal passes through
U13 to the Time Gate Flip-Flop, while the Channel A signal follows the same
path that it would in a frequency measurement. The measurement ends when
the function switch is placed to Stop. This causes the Gate Reset line to
High and set the Event Gate and Time Gate Flip-Flops.
The Ratio mode uses the same signal paths as the Totalize mode. That
is, Channel A signal is sent to the Event Scaler and Channel B signal is
sent to the Time Scaler.
Unlike Totalize, the Ratio measurement cycle is
based on a selected gate time; therefore, it is dependent on Gate Arm.
Since the Channel B signal is a direct replacement of the 500 MHz clock, the
lower the frequency of Channel B, the longer the measurement time.
In the Time Interval Mode, the Time Scaler will count 500 MHz clock
pulses only during the time between a Channel A pulse and a Channel B pulse.
The two input channels regulate the switching of the clock signal by
controlling the Event Gate Flip-Flop and Time Gate Flip Flop.
The Signal Gate is disabled, thereby enabling the Event Binary to
respond only to the output of U5.
A Channel A pulse enables U11 and U2
passes 500 MHz clock pulses to the Time Scaler. The output of U5 changes
the output state of U6A and allows U11B to pass the next incoming Channel B
pulse. The Channel B pulse enables U5 to clock the input of U4 to register
that one time interval has occurred. The next 500 MHz clock pulse disables
U2 from registering any more clock pulses.
c. Scalers.
Figure 5 is a block diagram of the Scalers (dividers)
which are each divide-by-ten stages.
When the Main Gate opens, the Event
Scaler begins accumulating event counts (Channel A pulses), and the Time
Scaler begins accumulating time counts (internal 500 MHz pulses).
Before
the decades can output their data, the accumulation of counts must end with
the conclusion of the gate time. A method for determining the end of the
gate time is therefore needed.
The front-panel Gate Time switch sends the Data Selector a different
4-line code for each of its switch positions. The code is passed through a
switch to the 4-16 Line Decoder, where it is decoded to a 16 line code.
This code addresses one of the Time Scaler decades to output its data. The
Time Scaler assumulates 500 MHz clock pulses until a "5" appears on the
output of the addressed decade: Any division of 500 MHz by a power
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