The first set of program codes is stored in the Word Doubler Storage
circuits until the second set is received. The two sets are then fed to the
Combinational Logic circuitry where the program codes combine to produce
about 50 command lines. Some of these command lines come directly from the
ROMs. As previously mentioned, the command lines control various assemblies
to perform particular functions. The results of the function are carried on
lines called qualifier lines. The combinational logic circuits generate the
qualifier signals that are sent to the Qualifier Select Logic.
The
Qualifier Select Logic examines only one qualifier line.
The line it
examines is determined by the 6-line output of Word Doubler Storage.
The Word Doubler Storage circuits provide 6 address lines from the
previously addressed program codes.
These six lines contain a two-digit
octal code, which performs two functions: (1) it provides the two most
significant digits of a 3-digit code, which will be used to address the ROMs
to the next address in the program, and (2) it selects the specific
qualifier line that the Qualifier Select Logic will output on the LSB (Least
Significant Bit) line. The LSB line is the third digit in the 3-digit ROM
address code.
Therefore, even though there is a definite arrangement of
address codes in a particular program, the program flow can be modified by
the state of the LSB line, which is the result of the last set of commands.
The internal time base for the counter is
supplied by a self contained 10 MHz, oven-controlled crystal oscillator
(figure 6).
A thermistor is used as the temperature sensing element to
maintain the crystal's ambient temperature at a constant value.
The unit
incorporates an AGCC circuit in the oscillator output to maintain the
amplitude of the output and; thereby, indirectly control the frequency. A
screwdriver adjustment is provided for this purpose.
Referring back to the block diagram, the 10 MHz signal feeds through a
pulse shaper and buffer to J2 on the rear panel (10 MHz Out), and to the
plug-in circuits. It also feeds into a times 50 multiplier circuit (X2, X5,
X5).
The result is a 500 MHz signal that is used as the counter's time
base.
Depending on the state of a status line, the 500 MHz clock may be
jittered to provide true time interval averaging. A portion of the signal
is tapped off through a buffer after the first X5 stage.
This 100 MHz
signal is fed to the Channel A & B Multiplexers to be used for self-check.
An external oscillator signal may be applied to J1, EXT FREQ STD INPUT.
This signal is sent through a circuit that phase locks the internal
oscillator to the external standard.
h. Display Assemblies.
The display assemblies (lower right of block
diagram and figure 7) combine the circuits necessary to display all
measurement data, minus sign and annunciators.
The digits are made up of
eleven seven-segment LEDs which are driven by the collector voltages of
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