of 10 is also a division of 1 second by the same power. Therefore, when a
"5" first appears on the output of the addressed decade, the elapsed time
(gate time) is the selected multiple of 1 second. For example, if 5 x 108
counts accumulate in 1 second (500 MHz), 1 ms will accumulate 5 x 105
counts. Once a 5 is detected, the main gate closes on the next Channel A
input pulse.
Each decade of the time and events scalers now contains one digit of
information, which can be sent to the processor as a 4-line code. This is
done by sequentially addressing each decade to output its stored data. The
address codes are supplied by the Denominator Register Counter (DRC) which
will be discussed later in this lesson.
d. Gate Control. Refer to the block diagram of figure 2 throughout the
following explanation.
The Gate Control circuits control the various
methods of arming the counter. Each of these methods must set the Arm Flip-
Flop, which remains set throughout the measurement phase.
The Resolution
Flip-Flop detects a 5 code from the Time Scaler switch, resets the Arm Flip-
Flop and signals the end of the measurement.
The front-panel reset
pushbutton resets the scalers, decades and gates after the end of the
processor cycle.
The processing cycle begins when the measurement cycle is complete and
the main gate closes. During a Totalize measurement, the process cycle is
not controlled by the main gate. There is no gate time in an accumulating
count and, therefore, no reason to sample a 5 code.
The scalers must be
periodically scanned, however, to update the display.
This is done by
automatically fixing the sample rate at 80 ms when the Function switch is
set to Start and using this signal to control the process cycle.
e. Arithmetic Processor. The data from the time and events scalers are
strobed into the Arithmetic Processor circuits, where the data is
manipulated in such a manner as to double the time data.
The
Adder/Subtractor circuits perform this operation by adding the time data to
itself.
This, in effect, produces a 1 GHz time base frequency.
This
results in keeping the measurement in terms of events/nanosecond.
Once this is accomplished, the Denominator Registor Counter (DRC)
strobes events data into the Denominator Register (DR). The events data is
now located in the DR and the doubled time data is located in the Numerator
Register (NR). This sequence of events occurs in every frequency, period or
time interval measurement.
The arithmetic process consists of dividing the contents of the DR
into the contents of the NR
.
For mainframe measurements involving a
gate time, the process is always a division. The contents of the registers,
therefore, may have to be exchanged, depending on the type of
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