(8) Variable Frequency Oscillator. Figure 11 is a schematic of the
VFO circuitry.
This circuit provides dial linearity, VFO control, and
contains the oscillator itself.
To maintain dial linearity over the entire range of the oscillator, a
string of resistors in the VFO linearizer (R8-R17) are added in line as the
dial setting is changed. Q1 and Q3 are a balanced pair with the base of Q3
at ground and the base of 01 containing the APC control voltage. Q2A and
02B are current sources for Q1 and Q3. When in the pulsed Rf mode, -15V is
applied to R7 which turns off the control circuit. Q4 is connected as an
emitter follower to provide isolation.
The VFO control assembly contains two voltage controlled varactor
diodes (CR1 and CR2) which shunt the VFO tuning capacitor to ground through
C1. The diodes are reverse biased such that an increase in bias decreases
capacitance and vice versa. Network CR3, R4 and C2 sets the limits of swing
on the VFO and provides an improved sinusoidal waveshape at the VFO input.
At the input to the VFO, Q1 and Q2 form a modified Colpitts oscillator
with a tank consisting of L1 and C2, and feedback capacitors C4 and C5. Q3
is a buffer to reduce the effect of load variations upon the oscillator.
Buffer amplifiers Q4-Q6 and Q5-Q7 are identical.
These are feedback type
circuits to drive the 50 ohm output line through transformers T1 and T2.
(9) Prescaler and Inhibit. The VFO output is fed to a differential
amplifier comprised by Q1 and Q2 (figure 12).
This amplified 67-133 MHz
signal is then directed to a Schmitt Trigger which sharpens the waveform for
the divide-by-two ICs U2 and U3.
The output of U3 is 1/4 the input
frequency. Q4 and Q7 amplify the divided frequency before it is directed to
the pulse driver.
The inhibit input from the level detector is applied to Q8.
In the
Pulsed RF mode, Q8 is cut off, there is no inhibit signal, and the prescaler
output is applied to the counter. In the APC mode, the inhibit signal is
present; Q8 is turned on, and the output signal at Q7 is shorted to ground.
When phase lock occurs in the APC mode, the inhibit signal again goes low,
Q8 is turned off and the prescaler output signal is applied to the counter.
(10) Gate Time Extender.
The purpose of the Gate Time Extender
(figure 13) is to send selected period pulses to the preset decade and
generate start and stop pulses to the plug-in adapter to determine the N
count.
The plug-in function switch on the front panel turns on Q1, its
collector rises to -15V supplying collector voltage to Q9 and Q10.
The
signal on the base of Q6 is low when the counter is counting and high when
displaying. This signal is inverted by Q6. When displaying, the
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